`timescale 1ns/1ns
module v8_data_rec_02(
    input  wire        resetb,
    input  wire        sclk,
    
    // set
    input  wire        set_d_ok,
    input  wire [15:0] set_addr,
    input  wire [7:0]  set_data,

    //PHY模块接口
    input  wire        mac_flag,
    input  wire [7:0]  mac_data,
    input  wire [1:0]  mac_vendor,//0:无效包 1：UDP
    input  wire        mac_error,
    
    //显示设置包
    output reg         disp_set_pkg_received,
    output reg  [7:0]  state,
    output reg  [7:0]  state_2,
    output reg  [7:0]  disp_contrast,
    output reg  [7:0]  disp_light,
    
    //
    input  wire        lock_enable,
    input  wire [31:0] lock,
    output reg         locked,

    // to led_display_top
    output reg           O_frame_start,
    output reg           O_frame_end,
    output reg           O_burst_start,
    output reg  [ 12: 0] O_burst_row,
    output reg  [ 12: 0] O_burst_col,
    output reg           O_pixel_en,
    output reg  [  7: 0] O_pixel_data,

    //
    output wire [7:0]  tout
);

/************************************************/
//        信号定义
/************************************************/
parameter  Preamble_OFFSET    = 23;
parameter  PACK_TYPE_FIRST    = 24 - Preamble_OFFSET;
parameter  PACK_DEPTH_FIRST   = 28 - Preamble_OFFSET;
parameter  HPACK_ADDR_START   = 30 - Preamble_OFFSET;
parameter  PACK_LOCK_FIRST    = 34 - Preamble_OFFSET;
parameter  PACK_LOCK_SECOND   = 35 - Preamble_OFFSET;
parameter  PACK_DATA_START    = 36 - Preamble_OFFSET;
parameter  SET_PACK_OFFSET    = PACK_DATA_START-2;

wire [5:0]  display_num;
reg  [10:0] mac_count;
reg         data_en_pre;
reg  [12:0] h_num_rec;
reg  [12:0] l_num_rec;
reg  [11:0] frame_pkg_period;
reg         received_frame_pkg_right_now;
reg         frame_busy;
reg         set_en;
reg         set_en_pre;
reg  [10:0] set_count;
reg  [3:0]  set_count_a_low;

/************************************************/
//        参数设置
/************************************************/
//always @(posedge sclk or negedge resetb)
//    if (resetb==0)
//        begin
//            display_num<=0;
//        end
//    else if (set_d_ok)
//        case (set_addr)
//            16'h0108:
//                begin
//                if(set_data==0)                 //与未加多屏功能的配置文件保持兼容
//                    display_num<= 0;     
//                else 
//                    display_num<=set_data-1'b1;
//                end             
//        endcase
assign display_num = 'd0;
   
/************************************************/
//        MAC数据计数
/************************************************/
always @(posedge sclk)
    if (mac_flag==0)
        mac_count<=0;
    else if (mac_count[10]==0)
        mac_count<=mac_count+1'b1;
                        
/************************************************/
//    显示数据包解析本地行号，总列号计算
/************************************************/
always @(posedge sclk)
    if (mac_flag==0)
        data_en_pre<=0;
    else if (mac_count==PACK_TYPE_FIRST && mac_data==8'hF5 && mac_vendor==1)
        data_en_pre<=1'b1;
        
always @(posedge sclk or negedge resetb)
    if (!resetb)
        begin
        h_num_rec<=0;
        l_num_rec<=0;
        end
    else if (data_en_pre==1)
        case (mac_count)
            HPACK_ADDR_START:      h_num_rec[7:0]<=mac_data;
            HPACK_ADDR_START+1:    h_num_rec[12:8]<=mac_data[4:0];
            HPACK_ADDR_START+2:    l_num_rec[7:0]<=mac_data;
            HPACK_ADDR_START+3:    l_num_rec[12:8]<=mac_data[4:0];
        endcase

/************************************************/
//        帧包处理
/************************************************/
always @(posedge sclk)
    if (O_frame_start)
        O_frame_start <= 1'b0;
    else if (mac_count==PACK_TYPE_FIRST && mac_data==8'hFA && mac_vendor==1 && !received_frame_pkg_right_now) // 帧包
        O_frame_start <= 1'b1;

always @(posedge sclk)
    if (O_frame_start)
        frame_pkg_period <= 12'hfff;
    else if (frame_pkg_period != 'd0)
        frame_pkg_period <= frame_pkg_period - 1'b1;

always @(posedge sclk)
    received_frame_pkg_right_now <= frame_pkg_period != 'd0;

always @(posedge sclk)
    if (O_frame_end)
        frame_busy <= 1'b0;
    else if (O_frame_start)
        frame_busy <= 1'b1;

always @(posedge sclk)
    if (O_frame_end)
        O_frame_end <= 1'b0;
    else if (frame_busy && mac_count==PACK_TYPE_FIRST && mac_data==8'hED && mac_vendor==1) // 空闲包
        O_frame_end <= 1'b1;
   
/************************************************/
//        输出
/************************************************/
always @(posedge sclk)
    if (O_burst_start)
        O_burst_start <=0;
    else if (data_en_pre==1 && mac_count==PACK_DATA_START - 1)
        O_burst_start <=1'b1;

always @(posedge sclk)
    if (mac_flag==0)
        O_pixel_en <=0;
    else if (data_en_pre==1 && mac_count==PACK_DATA_START)
        O_pixel_en <=1'b1;

always @(posedge sclk)
    if (locked)
        O_pixel_data <= 80;
    else
        O_pixel_data <= mac_data;

always @(posedge sclk)
    if (data_en_pre==1 && mac_count==PACK_DATA_START - 2)
        begin
        O_burst_row <= h_num_rec;
        O_burst_col <= l_num_rec;
        end

/************************************************/
//        显示设置包参数提取
/************************************************/
always @(posedge sclk)
    if (mac_flag==0)
        set_en_pre<=0;
    else if (mac_count == PACK_TYPE_FIRST && mac_data==8'hF0 && mac_vendor==1)
        set_en_pre<=1'b1;

always @(posedge sclk)
    set_count <= mac_count - SET_PACK_OFFSET[10:0];

always @(posedge sclk)
    if(set_count[10:4]==display_num)
        set_en<=1'b1;
    else
        set_en<=1'b0;

always @(*)
    set_count_a_low<=set_count[3:0]-1'b1;
                
always @(posedge sclk or negedge resetb)
    if (!resetb)
        begin
        state         <= 0;
        state_2       <= 0;
        disp_contrast <= 'h80;
        disp_light    <= 'h80;
        end
    else if (set_en_pre==1 && set_en==1) begin
        case (set_count_a_low[3:0])
            0: state         <= mac_data;
            1: state_2       <= mac_data;
            3: disp_contrast <= mac_data;
            4: disp_light    <= mac_data;
        endcase
    end
 
always @(posedge sclk or negedge resetb)
    if (!resetb)
        locked <= 1'b0;
    else if (lock_enable)
        begin
        if (set_en_pre==1 && set_en==1)
            begin
            if (set_count_a_low[3:0] == 0)
                locked <= 1'b0;
            else if (set_count_a_low[3:0] == 12 && mac_data != lock[31:24])
                locked <= 1'b1;
            else if (set_count_a_low[3:0] == 13 && mac_data != lock[23:16])
                locked <= 1'b1;
            else if (set_count_a_low[3:0] == 14 && mac_data != lock[15:8])
                locked <= 1'b1;
            else if (set_count_a_low[3:0] == 15 && mac_data != lock[7:0])
                locked <= 1'b1;
            end
        end
    else
        locked <= 1'b0;

always @(posedge sclk or negedge resetb)
    if (!resetb)
        disp_set_pkg_received <= 1'b0;
    else
        disp_set_pkg_received <= set_en_pre && !mac_flag;
 
/************************************************/
//        测试信号
/************************************************/
assign    tout=0;

endmodule        

